Bipolar transistors

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ESD protection, TVS, filtering and signal conditioning

MOSFETs

SiC MOSFETs

GaN FETs

IGBTs

Analog & Logic ICs

Automotive qualified products (AEC-Q100/Q101)

74AVCH2T45GT

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

The 74AVCH2T45 is a dual bit, dual supply transceiver that enables bidirectional level translation. It features two data input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are in the high-impedance OFF-state.

The 74AVCH2T45 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

Features and benefits

  • Wide supply voltage range: 0.8 V to 3.6 V for VCC(A) and VCC(B)

  • High noise immunity

  • Suspend mode

  • Bus hold on data inputs

  • Inputs accept voltages up to 3.6 V

  • Low noise overshoot and undershoot < 10 % of VCC

  • IOFF circuitry provides partial Power-down mode operation

  • Maximum data rates:

    • 500 Mbps (1.8 V to 3.3 V translation)

    • 320 Mbps (< 1.8 V to 3.3 V translation)

    • 320 Mbps (translate to 2.5 V or 1.8 V)

    • 280 Mbps (translate to 1.5 V)

    • 240 Mbps (translate to 1.2 V)

  • Latch-up performance exceeds 100 mA per JESD 78 Class II

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8-B (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3B exceeds 8000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Parametrics

Type number VCC(A) (V) VCC(B) (V) Logic switching levels Output drive capability (mA) tpd (ns) Nr of bits Power dissipation considerations Tamb (°C) Package name Category
74AVCH2T45GT 0.8 - 3.6 0.8 - 3.6 CMOS/LVTTL ± 12 2.1 2 very low -40~125 XSON8 Bi-directional | Direction controlled

PCB Symbol, Footprint and 3D Model

Model Name Description

Package

Type number Orderable part number, (Ordering code (12NC)) Status Marking Package Package information Reflow-/Wave soldering Packing
74AVCH2T45GT 74AVCH2T45GT,115
(935283722115)		 Active K45 SOT833-1
XSON8
(SOT833-1) 		SOT833-1 SOT833-1_115

Environmental information

Type number Orderable part number Chemical content RoHS RHF-indicator
74AVCH2T45GT 74AVCH2T45GT,115 74AVCH2T45GT rohs rhf rhf
Quality and reliability disclaimer

Series

Documentation (12)

File name Title Type Date
74AVCH2T45 Dual-bit, dual-supply voltage level translator/transceiver; 3-state Data sheet 2024-08-12
AN10161 PicoGate Logic footprints Application note 2002-10-29
AN90007 Pin FMEA for AVC family Application note 2018-11-30
Nexperia_document_guide_Logic_translators Nexperia Logic Translators Brochure 2021-04-12
Nexperia_document_guide_MiniLogic_MicroPak_201808 MicroPak leadless logic portfolio guide Brochure 2018-09-03
SOT833-1 3D model for products with SOT833-1 package Design support 2021-01-28
avch2t45 74AVCH2T45 Ibis model IBIS model 2014-10-14
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT833-1 plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm body Package information 2022-06-03
SOT833-1_115 XSON8; Reel pack for SMD, 7''; Q1/T1 product orientation Packing information 2020-04-21
74AVCH2T45GT_Nexperia_Product_Reliability 74AVCH2T45GT Nexperia Product Reliability Quality document 2024-06-16
MAR_SOT833 MAR_SOT833 Topmark Top marking 2013-06-03

Support

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Models

File name Title Type Date
avch2t45 74AVCH2T45 Ibis model IBIS model 2014-10-14
SOT833-1 3D model for products with SOT833-1 package Design support 2021-01-28

PCB Symbol, Footprint and 3D Model

Model Name Description

Ordering, pricing & availability

Type number Orderable part number Ordering code (12NC) Status Packing Packing Quantity Buy online
74AVCH2T45GT 74AVCH2T45GT,115 935283722115 Active SOT833-1_115 5,000 Order product

Sample

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If you do not have a direct account with Nexperia our network of global and regional distributors is available and equipped to support you with Nexperia samples. Check out the list of official distributors.

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

Interactive datasheet

Orderable parts

Type number Orderable part number Ordering code (12NC) Package Buy from distributors
74AVCH2T45GT 74AVCH2T45GT,115 935283722115 SOT833-1 Order product