74AUP1G00-Q100
Parametrics
| Type number | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Package name |
|---|---|---|---|---|---|---|---|---|---|
| 74AUP1G00GW-Q100 | 0.8 - 3.6 | CMOS | ± 1.9 | 8.3 | 70 | 1 | ultra low | -40~125 | TSSOP5 |
Package
| Type number | Orderable part number, (Ordering code (12NC)) | Status | Marking | Package | Package information | Reflow-/Wave soldering | Packing |
|---|---|---|---|---|---|---|---|
| 74AUP1G00GW-Q100 | 74AUP1G00GW-Q100H (935690852125) |
Active | pA |
TSSOP5 (SOT353-1) |
SOT353-1 |
WAVE_BG-BD-1
|
SOT353-1_125 |
Environmental information
| Type number | Orderable part number | Chemical content | RoHS | RHF-indicator |
|---|---|---|---|---|
| 74AUP1G00GW-Q100 | 74AUP1G00GW-Q100H | 74AUP1G00GW-Q100 |
|
|
Documentation (10)
| File name | Title | Type | Date |
|---|---|---|---|
| 74AUP1G00_Q100 | Low-power 2-input NAND gate | Data sheet | 2024-09-19 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT353-1 | 3D model for products with SOT353-1 package | Design support | 2019-09-23 |
| aup1g00 | 74AUP1G00 IBIS model | IBIS model | 2014-12-04 |
| Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Leaflet | 2019-04-12 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSSOP5_SOT353-1_mk | plastic, thin shrink small outline package; 5 leads; 0.65 mm pitch; 2 mm x 1.25 mm x 0.95 mm body | Marcom graphics | 2018-07-25 |
| SOT353-1 | plastic thin shrink small outline package; 5 leads; body width 1.25 mm | Package information | 2022-11-15 |
| Nexperia_Selection_guide_2023 | Nexperia Selection Guide 2023 | Selection guide | 2023-05-10 |
| WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
Support
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Ordering, pricing & availability
Sample
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