74LVC1G74-Q100
Single D-type flip-flop with set and reset; positive edge trigger
The 74LVC1G74-Q100 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 1.65 V to 5.5 V
Overvoltage tolerant inputs to 5.5 V
High noise immunity
±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Direct interface with TTL levels
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 250 mA
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Parametrics
| Type number | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Package name |
|---|---|---|---|---|---|---|---|---|
| 74LVC1G74DC-Q100 | 1.65 - 5.5 | CMOS/LVTTL | ± 32 | 3.5 | 280 | low | -40~125 | VSSOP8 |
| 74LVC1G74DP-Q100 | 1.65 - 5.5 | CMOS/LVTTL | ± 32 | 3.5 | 280 | low | -40~125 | TSSOP8 |
| 74LVC1G74GT-Q100 | 1.65 - 5.5 | CMOS/LVTTL | ± 32 | 3.5 | 280 | low | -40~125 | XSON8 |
Package
| Type number | Orderable part number, (Ordering code (12NC)) | Status | Marking | Package | Package information | Reflow-/Wave soldering | Packing |
|---|---|---|---|---|---|---|---|
| 74LVC1G74DC-Q100 | 74LVC1G74DC-Q100H (935299293125) |
Active | V74 |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 | |
| 74LVC1G74DP-Q100 | 74LVC1G74DP-Q100H (935299294125) |
Active | V74 |
TSSOP8 (SOT505-2) |
SOT505-2 | SOT505-2_125 | |
| 74LVC1G74GT-Q100 | 74LVC1G74GT-Q100X (935299297115) |
Active | V74 |
XSON8 (SOT833-1) |
SOT833-1 | SOT833-1_115 |
Environmental information
| Type number | Orderable part number | Chemical content | RoHS | RHF-indicator |
|---|---|---|---|---|
| 74LVC1G74DC-Q100 | 74LVC1G74DC-Q100H | 74LVC1G74DC-Q100 |
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| 74LVC1G74DP-Q100 | 74LVC1G74DP-Q100H | 74LVC1G74DP-Q100 |
|
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| 74LVC1G74GT-Q100 | 74LVC1G74GT-Q100X | 74LVC1G74GT-Q100 |
|
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Documentation (16)
| File name | Title | Type | Date |
|---|---|---|---|
| 74LVC1G74_Q100 | Single D-type flip-flop with set and reset; positive edge trigger | Data sheet | 2023-08-18 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| Nexperia_document_guide_MiniLogic_MicroPak_201808 | MicroPak leadless logic portfolio guide | Brochure | 2018-09-03 |
| SOT765-1 | 3D model for products with SOT765-1 package | Design support | 2020-01-22 |
| SOT505-2 | 3D model for products with SOT505-2 package | Design support | 2019-01-18 |
| SOT833-1 | 3D model for products with SOT833-1 package | Design support | 2021-01-28 |
| lvc1g74 | 74LVC1G74 IBIS model | IBIS model | 2014-10-20 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| VSSOP8_SOT765-1_mk | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Marcom graphics | 2017-01-28 |
| SOT765-1 | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Package information | 2022-06-03 |
| SOT505-2 | plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm body | Package information | 2022-06-03 |
| SOT833-1 | plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm body | Package information | 2022-06-03 |
| Nexperia_Selection_guide_2023 | Nexperia Selection Guide 2023 | Selection guide | 2023-05-10 |
| MAR_SOT833 | MAR_SOT833 Topmark | Top marking | 2013-06-03 |
Support
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Models
| File name | Title | Type | Date |
|---|---|---|---|
| SOT765-1 | 3D model for products with SOT765-1 package | Design support | 2020-01-22 |
| SOT505-2 | 3D model for products with SOT505-2 package | Design support | 2019-01-18 |
| SOT833-1 | 3D model for products with SOT833-1 package | Design support | 2021-01-28 |
| lvc1g74 | 74LVC1G74 IBIS model | IBIS model | 2014-10-20 |
Ordering, pricing & availability
Sample
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