74AUP2G79-Q100
Parametrics
Type number | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Package name |
---|---|---|---|---|---|---|---|---|
74AUP2G79DC-Q100 | 0.8 - 3.6 | CMOS | ± 1.9 | 8.5 | 400 | ultra low | -40~125 | VSSOP8 |
Package
Type number | Orderable part number, (Ordering code (12NC)) | Status | Marking | Package | Package information | Reflow-/Wave soldering | Packing |
---|---|---|---|---|---|---|---|
74AUP2G79DC-Q100 | 74AUP2G79DC-Q100H (935301664125) |
Active | p79 |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 |
Environmental information
Type number | Orderable part number | Chemical content | RoHS | RHF-indicator |
---|---|---|---|---|
74AUP2G79DC-Q100 | 74AUP2G79DC-Q100H | 74AUP2G79DC-Q100 |
Documentation (11)
File name | Title | Type | Date |
---|---|---|---|
74AUP2G79_Q100 | Low-power dual D-type flip-flop; positive-edge trigger | Data sheet | 2023-07-18 |
AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
AN11052 | Pin FMEA for AUP family | Application note | 2019-01-09 |
Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
SOT765-1 | 3D model for products with SOT765-1 package | Design support | 2020-01-22 |
aup2g79 | aup2g79 IBIS model | IBIS model | 2013-04-07 |
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Leaflet | 2019-04-12 |
Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
VSSOP8_SOT765-1_mk | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Marcom graphics | 2017-01-28 |
SOT765-1 | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Package information | 2022-06-03 |
Nexperia_Selection_guide_2023 | Nexperia Selection Guide 2023 | Selection guide | 2023-05-10 |
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Ordering, pricing & availability
Sample
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