74LVC3G07-Q100
Triple buffer with open-drain output
The 74LVC3G07-Q100 provides three non-inverting buffers.
The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.
Input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V).
-24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Parametrics
Type number | VCC (V) | Logic switching levels | Output drive capability (mA) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Package name |
---|---|---|---|---|---|---|---|---|
74LVC3G07DC-Q100 | 1.65 - 5.5 | CMOS/LVTTL | 32 | 175 | 3 | low | -40~125 | VSSOP8 |
74LVC3G07DP-Q100 | 1.65 - 5.5 | CMOS/LVTTL | 32 | 175 | 3 | low | -40~125 | TSSOP8 |
Package
Type number | Orderable part number, (Ordering code (12NC)) | Status | Marking | Package | Package information | Reflow-/Wave soldering | Packing |
---|---|---|---|---|---|---|---|
74LVC3G07DC-Q100 | 74LVC3G07DC-Q100H (935300248125) |
Active | V07 |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 | |
74LVC3G07DP-Q100 | 74LVC3G07DP-Q100H (935300249125) |
Active | V07 |
TSSOP8 (SOT505-2) |
SOT505-2 | SOT505-2_125 |
Environmental information
Type number | Orderable part number | Chemical content | RoHS | RHF-indicator |
---|---|---|---|---|
74LVC3G07DC-Q100 | 74LVC3G07DC-Q100H | 74LVC3G07DC-Q100 | ||
74LVC3G07DP-Q100 | 74LVC3G07DP-Q100H | 74LVC3G07DP-Q100 |
Documentation (12)
File name | Title | Type | Date |
---|---|---|---|
74LVC3G07_Q100 | Triple buffer with open-drain output | Data sheet | 2023-08-24 |
AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
SOT765-1 | 3D model for products with SOT765-1 package | Design support | 2020-01-22 |
SOT505-2 | 3D model for products with SOT505-2 package | Design support | 2019-01-18 |
lvc3g07 | 74LVC3G07 IBIS model | IBIS model | 2015-01-15 |
Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
VSSOP8_SOT765-1_mk | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Marcom graphics | 2017-01-28 |
SOT765-1 | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Package information | 2022-06-03 |
SOT505-2 | plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm body | Package information | 2022-06-03 |
Nexperia_Selection_guide_2023 | Nexperia Selection Guide 2023 | Selection guide | 2023-05-10 |
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