Bipolar transistors

Diodes

ESD protection, TVS, filtering and signal conditioning

MOSFETs

SiC MOSFETs

GaN FETs

IGBTs

Analog & Logic ICs

Automotive qualified products (AEC-Q100/Q101)

74AUP1T97GF

Low-power configurable gate with voltage-level translator

The 74AUP1T97 is a configurable multiple function gate with level translating, Schmitt-trigger inputs. The device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. Low threshold Schmitt trigger inputs allow these devices to be driven by 1.8 V logic levels in 3.3 V applications. This device ensures very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Not recommended for new designs (NRND).

Features and benefits

  • Wide supply voltage range from 2.3 V to 3.6 V

  • CMOS low power dissipation

  • High noise immunity

  • Overvoltage tolerant inputs to 3.6 V

  • Low noise overshoot and undershoot < 10 % of VCC

  • IOFF circuitry provides partial power-down mode operation

  • Latch-up performance exceeds 100 mA per JESD 78 Class II

  • Low static power consumption; ICC = 1.5 μA (maximum)

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8C (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Parametrics

Type number Package name
74AUP1T97GF
XSON6

PCB Symbol, Footprint and 3D Model

Model Name Description

Series

Documentation (12)

File name Title Type Date
74AUP1T97 Low-power configurable gate with voltage-level translator Data sheet 2023-07-17
AN10161 PicoGate Logic footprints Application note 2002-10-29
Nexperia_document_guide_Logic_translators Nexperia Logic Translators Brochure 2021-04-12
Nexperia_document_guide_MiniLogic_MicroPak_201808 MicroPak leadless logic portfolio guide Brochure 2018-09-03
SOT891 3D model for products with SOT891 package Design support 2019-10-03
aup1t97 aup1t97 IBIS model IBIS model 2015-09-06
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Leaflet 2019-04-12
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
DFN1010-6_SOT891_mk plastic, extremely thin small outline package; 6 terminals; 0.55 mm pitch; 1 mm x 1 mm x 0.5 mm body Marcom graphics 2017-01-28
SOT891 plastic, leadless extremely thin small outline package; 6 terminals; 0.35 mm pitch; 1 mm x 1 mm x 0.5 mm body Package information 2020-04-21
REFLOW_BG-BD-1 Reflow soldering profile Reflow soldering 2021-04-06
MAR_SOT891 MAR_SOT891 Topmark Top marking 2013-06-03

Support

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Models

File name Title Type Date
aup1t97 aup1t97 IBIS model IBIS model 2015-09-06
SOT891 3D model for products with SOT891 package Design support 2019-10-03

PCB Symbol, Footprint and 3D Model

Model Name Description

Ordering, pricing & availability

Sample

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How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

Interactive datasheet