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74AXP1T125GS

Dual supply buffer/line driver; 3-state

The 74AXP1T125 is a dual supply non-inverting buffer/line driver with 3-state output. It features one input (A), an output (Y), an output enable input (OE) and dual supply pins (VCCI and VCCO). A HIGH level at pin OE causes the output to assume a high-impedance OFF-state. The inputs are referenced to VCCI and the output is referenced to VCCO. All inputs can be connected directly to VCCI or GND. VCCI can be supplied at any voltage between 0.7 V and 2.75 V and VCCO can be supplied at any voltage between 1.2 V and 5.5 V. This feature allows voltage level translation.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device ensures very low static and dynamic power consumption across the entire supply range and is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

This product has been discontinued

Features and benefits

  • Wide supply voltage range:

    • VCCI: 0.7 V to 2.75 V

    • VCCO: 1.2 V to 5.5 V

  • Low input capacitance; CI = 0.6 pF (typical)

  • Low output capacitance; CO = 1.8 pF (typical)

  • Low dynamic power consumption; CPD = 0.4 pF at VCCI = 1.2 V (typical)

  • Low dynamic power consumption; CPD = 7.1 pF at VCCO = 3.3 V (typical)

  • Low static power consumption; ICCI = 0.5 μA (85 °C maximum)

  • Low static power consumption; ICCO = 1.8 μA (85 °C maximum)

  • High noise immunity

  • Complies with JEDEC standard:

    • JESD8-12A.01 (1.1 V to 1.3 V; A, OE inputs)

    • JESD8-11A.01 (1.4 V to 1.6 V)

    • JESD8-7A (1.65 V to 1.95 V)

    • JESD8-5A.01 (2.3 V to 2.7 V)

    • JESD8-C (2.7 V to 3.6 V; Y output)

    • JESD12-6 (4.5 V to 5.5 V; Y output)

  • ESD protection:

    • HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV

    • CDM JESD22-C101E exceeds 1000 V

  • Latch-up performance exceeds 100 mA per JESD78D Class II

  • Inputs accept voltages up to 2.75 V

  • Low noise overshoot and undershoot < 10% of VCCO

  • IOFF circuitry provides partial power-down mode operation

  • Multiple package options

  • Specified from -40 °C to +85 °C

Parametrics

Type number VCC(A) (V) VCC(B) (V) Logic switching levels Output drive capability (mA) tpd (ns) Nr of bits Power dissipation considerations Tamb (°C)
74AXP1T125GS 0.7 - 2.75 1.2 - 5.5 CMOS ± 12 4.7 1 ultra low -40~85

Package

All type numbers in the table below are discontinued.

Type number Orderable part number, (Ordering code (12NC)) Status Marking Package Package information Reflow-/Wave soldering Packing
74AXP1T125GS 74AXP1T125GSH
(935306987125)		 Obsolete no package information

Environmental information

All type numbers in the table below are discontinued.

Type number Orderable part number Chemical content RoHS RHF-indicator
74AXP1T125GS 74AXP1T125GSH 74AXP1T125GS rohs rhf rhf
Quality and reliability disclaimer

Series

Documentation (6)

File name Title Type Date
74AXP1T125 Dual supply buffer/line driver; 3-state Data sheet 2021-11-03
AN90029 Pin FMEA for AXPnT family Application note 2021-07-13
Nexperia_document_guide_Logic_translators Nexperia Logic Translators Brochure 2021-04-12
axp1t125 74AXP1T125 IBIS model IBIS model 2016-03-02
Nexperia_document_leaflet_Logic_AXP_technology_portfolio_201904 AXP – Extremely low-power logic technology portfolio Leaflet 2019-04-05
74AXP1T125GS_Nexperia_Product_Reliability 74AXP1T125GS Nexperia Product Reliability Quality document 2022-05-04

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Models

File name Title Type Date
axp1t125 74AXP1T125 IBIS model IBIS model 2016-03-02

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