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Analog & Logic ICs

Automotive qualified products (AEC-Q100/Q101)

74LVC1T45GF

Dual supply translating transceiver; 3-state

The 74LVC1T45; 74LVCH1T45 are single bit, dual supply transceivers with 3-state outputs that enable bidirectional level translation. They feature two 1-bit input-output ports (A and B), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2 V and 5.5 V making the device suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins A and DIR are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to A.

The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A port and B port are in the high-impedance OFF-state.

Active bus hold circuitry in the 74LVCH1T45 holds unused or floating data inputs at a valid logic level.

Not recommended for new designs (NRND).

Alternatives

Features and benefits

  • Wide supply voltage range:

    • VCC(A): 1.2 V to 5.5 V

    • VCC(B): 1.2 V to 5.5 V

  • High noise immunity

  • Maximum data rates:

    • 420 Mbps (3.3 V to 5.0 V translation)

    • 210 Mbps (translate to 3.3 V))

    • 140 Mbps (translate to 2.5 V)

    • 75 Mbps (translate to 1.8 V)

    • 60 Mbps (translate to 1.5 V)

  • Suspend mode

  • Latch-up performance exceeds 100 mA per JESD 78 Class II

  • ±24 mA output drive (VCC = 3.0 V)

  • Inputs accept voltages up to 5.5 V

  • Low power consumption: 16 μA maximum ICC

  • IOFF circuitry provides partial Power-down mode operation

  • Complies with JEDEC standards:

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8C (2.7 V to 3.6 V)

    • JESD36 (4.5 V to 5.5 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 4000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Parametrics

Type number Package name
74LVC1T45GF
XSON6

PCB Symbol, Footprint and 3D Model

Model Name Description

Series

Documentation (12)

File name Title Type Date
74LVC_LVCH1T45 Dual supply translating transceiver; 3-state Data sheet 2023-08-04
AN10161 PicoGate Logic footprints Application note 2002-10-29
AN11009 Pin FMEA for LVC family Application note 2019-01-09
Nexperia_document_guide_Logic_translators Nexperia Logic Translators Brochure 2021-04-12
Nexperia_document_guide_MiniLogic_MicroPak_201808 MicroPak leadless logic portfolio guide Brochure 2018-09-03
SOT891 3D model for products with SOT891 package Design support 2019-10-03
lvc1t45 lvc1t45 IBIS model IBIS model 2013-04-08
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
DFN1010-6_SOT891_mk plastic, extremely thin small outline package; 6 terminals; 0.55 mm pitch; 1 mm x 1 mm x 0.5 mm body Marcom graphics 2017-01-28
SOT891 plastic, leadless extremely thin small outline package; 6 terminals; 0.35 mm pitch; 1 mm x 1 mm x 0.5 mm body Package information 2020-04-21
REFLOW_BG-BD-1 Reflow soldering profile Reflow soldering 2021-04-06
MAR_SOT891 MAR_SOT891 Topmark Top marking 2013-06-03

Support

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Models

File name Title Type Date
lvc1t45 lvc1t45 IBIS model IBIS model 2013-04-08
SOT891 3D model for products with SOT891 package Design support 2019-10-03

PCB Symbol, Footprint and 3D Model

Model Name Description

Ordering, pricing & availability

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Interactive datasheet