74AUP1T97-Q100
Parametrics
| Type number | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Package name |
|---|---|---|---|---|---|---|---|---|---|
| 74AUP1T97GW-Q100 | 2.3 - 3.6 | CMOS | ± 4 | 3.9 | 70 | 1 | ultra low | -40~125 | TSSOP6 |
Package
| Type number | Orderable part number, (Ordering code (12NC)) | Status | Marking | Package | Package information | Reflow-/Wave soldering | Packing |
|---|---|---|---|---|---|---|---|
| 74AUP1T97GW-Q100 | 74AUP1T97GW-Q100H (935691179125) |
Active | 59 |
TSSOP6 (SOT363-2) |
SOT363-2 | SOT363-2_125 |
Environmental information
| Type number | Orderable part number | Chemical content | RoHS | RHF-indicator |
|---|---|---|---|---|
| 74AUP1T97GW-Q100 | 74AUP1T97GW-Q100H | 74AUP1T97GW-Q100 |
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Documentation (6)
| File name | Title | Type | Date |
|---|---|---|---|
| 74AUP1T97_Q100 | Low-power configurable gate with voltage-level translator | Data sheet | 2023-07-17 |
| Nexperia_document_guide_Logic_translators | Nexperia Logic Translators | Brochure | 2021-04-12 |
| SOT363-2 | 3D model for products with SOT363-2 package | Design support | 2023-02-02 |
| Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Leaflet | 2019-04-12 |
| Nexperia_document_leaflet_Logic_X2SON_packages_062018 | X2SON ultra-small 4, 5, 6 & 8-pin leadless packages | Leaflet | 2018-06-05 |
| SOT363-2 | plastic thin shrink small outline package; 6 leads; body width 1.25 mm | Package information | 2022-11-21 |
Support
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Models
| File name | Title | Type | Date |
|---|---|---|---|
| SOT363-2 | 3D model for products with SOT363-2 package | Design support | 2023-02-02 |
Ordering, pricing & availability
Sample
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