Webinar: Automotive ESD Protection

The transmission line pulse (TLP) is a short-duration rectangular pulse in a controlled impedance environment of 50Ω, which improves test accuracy and measurement reproducibility.

TLP characterizes performance attributes of devices under stresses that have a short pulse width and fast rise time. Each measurement result becomes a point on the TLP graph that shows a TLP I-V characteristic, i.e. the TLP-curve.

Nexperia automotive grades products are AEC-Q101 qualified if indicated in the datasheet. The ESD devices show very low self-heating since no power is applied. In addition, Nexperia performs several reliability tests according to JEDEC and ISO norms to ensure high reliability.

Basically, there a two ESD failure modes: destructive where the device is damaged and non-destructive which show soft failure. Non-destructive failures are hard to detect but it helps to perform tests under incrementally higher voltages to determine destructive failure point. As such, sometimes degradation of the device can be detected early which provides a first indication of potential risk. Deviation of leakage current gives also a good indication.

For 24 V DC power line, a reverse standoff voltage of min. 32 V is required due to jump start requirements

SEED (System Efficient ESD Design) simulation is an effective approach to simulate an ESD event. It especially helps to match an IC with discrete ESD protection. For further introduction, we recommend our white paper describing the concept and basic steps.

The ESD design strategy is independent due to general ESD design aspects. However, additional requirements may narrow the range of suitable protection devices and include further tests. For instance, the ISO10605 states additional tests for automotive applications.

Nexperia automotive grades products are AEC-Q101 qualified if indicated in the datasheet. All of our products are considered basic building blocks, where the functional safety criticality is defined by the system. This is important as a default failure mode for one device/system may not be suitable for another, and is the reason why we cannot assume any ASIL rating based on the ISO26262 methodology. Nexperia can provide further details and support to customers who will use ESD protection devices in safety critical applications.

Scattering parameters can be included in datasheets depending on application and protection device. S-Parameter data can be send via e-mail on demand.

For sub GHz applications, the ESD protection device capacitance shows major impact on impedance. To improve impedance curve, a lower capacitance device may improve performance. The package has a minor impact in this area.

Cross talk depends on the sub-system. As PCB designs become smaller and show a higher density of traces, there might be a higher risk of cross talk. However, this is more on the PCB surface and not the periphery.

If using just a capacitor, the ESD pulse might be damped a little but the system level protection is very low. A discrete ESD protection device adds significant improvement of system level ESD robustness and increase system reliability.

The conducted discharge on the connector is only minor impacted by the housing of the module you are designing. The air discharge is very strongly depending the housing and, hence, should be considered during development.

For DFN package soldering and AOI guidelines, please refer to Nexperia application notes.

In this example with PCB having 4 or more layers, the GND layer is just below the top layer with a prepreg of around 100 µm. So the via inductance of 100µm is small. However, depending on your PCB stack up you may route your GND pin differently.

Coax (single ended) or differential transmission has not a real impact on the electrical performance of the ESD protection device. It might impact the package of your protections device, since you need to decide how many lines you have to protect.

We are currently working on eye diagram measurements and simulations for other applications besides USBx and HDMIx.

A TLP curve comparison provides a quick indication for this. As such, the ESD protection device should trigger before the internal ESD protection of the PHY. For instance, a good match would be if the breakdown voltage of the ESD protection is 35 V and the breakdown voltage of the PHY is 60 V. In this combination, the ESD protection clamps first and takes the vast majority of ESD pulse.

There might be some issues related to DPI test. Those are, when too much energy is getting absorbed by the network during the test. In such case you need to choose a ESD protection device with higher trigger voltage.

The traces should be routed directly to the ESD protection device without changing layer or coupling to other PCB structure. However, the routing depends strongly on the sub-application and cannot be covered in datasheets.

All Nexperia packages fulfil AEC-Q101 and other, highest quality standards.

The reason is the during the DPI test RF noise can achieve amplitudes up to 100 V. To avoid clamping of the ESD protection device, the triggering voltage was defined to be >100 V. The DC voltage over 24 V is related to the short to battery requirement (similar as for CAN/LIN).

For some application such as LIN/CAN/Ethernet the 3-pin package does not impact the signal integrity significantly. For high frequency applications such as SerDes and Multimedia we recommend other, e.g. leadless packages.

For 1000BASE-T1 the PESD2ETH1G-T can be used with even smaller parasitic capacitance (<2 pF). For further product information use the selection guide on the webpage.

By an eye diagram you can judge if the ESD protection is impacting your digital system too much or not. Besides S-parameters and parasitic capacitance, this is another view on the signal integrity on device level.

For CAN it is more importance to look on the capacitance. However, for some CAN products Nexperia also provides S-parameters for CAN products.

For further product information please visit our webpage