Webinar: Fundamentals of ESD Protection

At Nexperia we focus on device modelling including SPICE models. However, we do not use SPICE models considering air gaps due to poor repeatability of results. Models with contact discharge and optimized signal integrity show better measurement quality. For even better insights, we recommend to use SEED simulation representing the application and ESD event very precisely.

The maximum resistance is always given by the application. You should try without additional resistance in the beginning. If you see that you cannot reach the target ESD level, you have to evaluate how much the application allows you to add and, try if this is sufficient.

Throughout history, new ESD protection technologies were developed. First, people used large capacitors, but they have extremely bad clamping behaviour and are not applicable for data lines. Next, Zener diodes were used and optimized. This can be applied to both internal IC as well as external ESD protection. The main target is to reduce the clamping voltage to lower the ESD stress within the IC and system. New approaches such as "snap-back" behaviour offer a great protection behaviour to lower the clamping voltage. In addition, new materials and structures can be considered and help to improve the device level robustness for assembly but also the more important system level robustness.

The clamping voltage can be lower than breakdown voltage due to protection behaviours where the clamping voltage is actively lowered. The "snap-back" technology is a great example. A lower clamping voltage offers better system level protection and is not a disadvantage.

The gradient of the tangent in the operating point (OP) provides the dynamic resistance Rdyn (TLP). Rdyn (TLP) is determined for reverse and forward directions of the DUT. In fact of the linear behaviour V = f(I), the tangent in the operating point can be approximated via the trendline Linear VCL (TLP) = f(I) and hence provides the dynamic resistance Rdyn (TLP).

The relative deviation of capacitance of separate ESD protection devices is almost the same. For instance, a 20 pF device for CAN bus shows about the same relative capacitance deviation as a 2 pF solution for Ethernet protection. As such, the absolute capacitance deviation becomes smaller if the device capacitance is lower. In this case, a 2 pF solution would show only 0.2 pF deviation (10% relative) showing minor impact on signal integrity and performance.

The reverse working maximum voltage VRWM indicates the DC voltage that can be applied without the device being active in order to not interrupt normal operation mode. The breakdown voltage VBR is higher compared to the VRWM and describes the transition of non-operating to operating mode. This can be also seen at the stated current. Therefore, there is a gap between both voltages to ensure safe operation.

On the shown PCB, the ground connection is on the upper left. Thus, in case of the ESD event with external ESD protection, the current flows through the protection device directly to ground as the ESD protection functions as a current divider. Without external ESD protection, the ESD pulse can flow directly through the traces into the IC causing malfunction and less current flows to ground.

Power dissipation is the product of clamping voltage times peak pulse current: P = U x I. For instance, IPP = 5 A and VCL = 41 V would result in 205 W. Important to mention is that you can only draw limited information about the robustness and do not learn about the system level robustness. In case of a "snap-back" protection behaviour where the clamping voltage is actively lowered, the power dissipation would be lower as well. This can be confusing since the "snap-back" behaviour offers superior ESD protection. Therefore, the power dissipation does not provide a good indication of ESD robustness.

Basically, everything can be destroyed but it is difficult to detect the exact root cause once the device is fully destroyed. To reconstruct the failure mode, a disruptive physical analysis and further investigation including SEED simulation can help.

The parameters clamping voltage and peak pulse current provide a good indication of ESD protection. A low clamping voltage will, in effect, lower the shoulder of the ESD waveform. Different ESD protection technologies such as open-base transistors or thyristors with a "snap-back" behaviour can improve further.

SEED (System Efficient ESD Design) simulation is an effective approach to simulate an ESD event. It especially helps to match an IC with discrete ESD protection. For further introduction, we recommend our white paper describing the concept and basic steps.

An EMI scanner can be used to measure the magnetic field and current flow on the PCB in case of ESD event. It operates with a near field probe which is positioned above the circuit. The duration ESD Event is roughly 100 ns. The EMI scanner cannot simulate but records a video of the PCB under test. The blue colour indicates low current density where the yellow or red colour indicates high current density. As such, it is possible to get a visual insight of ESD concept effectivity.

Temperature is a major factor for derating parameters, however, silicon based ESD protection is characterized by minor performance loss over temperature. Thermal robustness is usually provided in the datasheet for a typical PCB stackup.

The main difference is the topology. The snap back devices have the open base or silicon controlled rectifier topology. Both of them allow to snap back which results in significant clamping voltage reduction. In comparison, a Zener protection starts to clamp when the breakdown voltage is achieved and clamping voltage is increasing slowly. All typologies should be considered when choosing an ESD protection device, though, for high-speed lines a snap-back typology will increase performance significantly.

It is possible to stack ESD protection devices in series. If you place two times the same ESD protection in series, the following happens:

• VRWM is doubled
• Trigger / breakdown is doubled
• Vclamping is doubled
• CD is halved

Nexperia offers consultancy and evaluation support on customer request. Extra cost may arise on an individual basis for e.g. special test boards. Please reach out to your Nexperia contact for further details.

Usually, the ESD protection devices survive a reasonable amount of ESD pulses very well, without degradation. Thermal issues should be considered when a longer duration surge pulses are applied.

If a snap-back device is triggered, a latch-up can happen if the on-state current is higher than the hold current of the ESD protection device. However, most ESD protection devices withstand the current arising from this condition: Nexperia parts were tested in latch-up with 100mA for several hours without showing any damage or degradation. If an interface is affected, a soft fail occurs but no hardware fail. For many interfaces, the snap-back device automatically returns to its off-state once the affected data line is in single-ended low state.

Nexperia uses industry proven mold compounds that fulfil all automotive quality requirements such as AEC-Q101 or MSL levels. Damage caused by electrical overstress (EOS) can be prevented by application design. In addition, a high IPPM value can increase safety margin on device level.

ESD protection devices are usually robust devices. However, the environmental impacts usually are covered by qualifications tests, such as AEC-Q101 or similar.

Usually, the forward voltage of ESD protection devices is not of importance for ESD purposes. However, this information can be shared with you on demand.

While applying repeating spikes the device might be heated up. The increasing temperature will for sure impact the electrical behaviour, such as the break down voltage. We provide a measurement data over temperature on demand.

The cross talk of ESD events is strongly dependent on your sub-application including the PCB, its stack-up etc. So, we cannot give a specific recommendation.

The IC are typically robust for HBM up to 2kV. Or at least 500V. In addition, this is the first peak with has a duration of a few nanoseconds only. There is not much energy in this strike, and hence, usually not a problem for classic networks. It can be a problem for very sensitive, e.g. high speed ICs. Therefore, we suggest to use ESD devices with very low trigger and clamping voltage and, in addition with smallest parasitics, e.g. leadless packages, as discussed during the second session.

Quality requirements from customers may deviate due to individual assembly guidelines and special quality aspects. Nexperia offers dedicated product groups to fulfil highest quality standards above AEC-Q101.

The ESD protection should always be placed close to the connector in order to work as current divider and clamp the ESD current to ground. Depending on board net voltage, a higher VBR must be considered. For instance, for a 24 V board net, a VBR of >32 V should be chosen.

The trigger voltage is more determined by the physical structure of the ESD device but the dynamic resistance has a minor impact on the triggering behaviour as well.

Nexperia provides a parametric search to filter certain parameters on our webpage.