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Click here for more information74AUP1G373GN
Low-power D-type transparent latch; 3-state
The 74AUP1G373 is a single D-type transparent latch; 3-state. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
CMOS low power dissipation
Low static power consumption; ICC = 0.9 μA (maximum)
Overvoltage tolerant inputs to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
Parametrics
Type number | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | Power dissipation considerations | Tamb (°C) | Package name |
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74AUP1G373GN | 0.8 - 3.6 | CMOS | 1.9/-1.9 | 8.5 | ultra low | -40~125 | XSON6 |
PCB Symbol, Footprint and 3D Model
Model Name | Description |
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Series
Documentation (12)
File name | Title | Type | Date |
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74AUP1G373 | Low-power D-type transparent latch; 3-state | Data sheet | 2023-07-13 |
AN11052 | Pin FMEA for AUP family | Application note | 2019-01-09 |
Nexperia_document_guide_MiniLogic_MicroPak_201808 | MicroPak leadless logic portfolio guide | Brochure | 2018-09-03 |
SOT1115 | 3D model for products with SOT1115 package | Design support | 2023-02-02 |
aup1g373 | aup1g373 IBIS model | IBIS model | 2014-12-21 |
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Leaflet | 2019-04-12 |
Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
XSON6_SOT1115_mk | plastic, extremely thin small outline package; 6 terminals; 0.55 mm pitch; 0.9 mm x 1 mm x 0.35 mm body | Marcom graphics | 2017-01-28 |
SOT1115 | plastic, leadless extremely thin small outline package; 6 terminals; 0.3 mm pitch; 0.9 mm x 1 mm x 0.35 mm body | Package information | 2022-05-27 |
74AUP1G373GN_Nexperia_Product_Reliability | 74AUP1G373GN Nexperia Product Reliability | Quality document | 2024-06-16 |
REFLOW_BG-BD-1 | Reflow soldering profile | Reflow soldering | 2021-04-06 |
MAR_SOT1115 | MAR_SOT1115 Topmark | Top marking | 2013-06-03 |
Support
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PCB Symbol, Footprint and 3D Model
Model Name | Description |
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Ordering, pricing & availability
Sample
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.