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Analog & Logic ICs

Automotive qualified products (AEC-Q100/Q101)

74LVCH16373ADL

16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches with 3-state outputs. The devices can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The devices feature two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When nLE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Bus hold on the data inputs eliminates the need for external pull-up resistors to hold unused inputs.

This product has been discontinued

Alternatives

Features and benefits

  • Overvoltage tolerant inputs to 5.5 V

  • Wide supply voltage range from 1.2 V to 3.6 V

  • CMOS low power dissipation

  • MULTIBYTE flow-through standard pinout architecture

  • Multiple low inductance supply pins for minimum noise and ground bounce

  • Direct interface with TTL levels

  • All data inputs have bus hold (74LVCH16373A only)

  • IOFF circuitry provides partial Power-down mode operation

  • Complies with JEDEC standards:
    • JESD8-7A (1.65 V to 1.95 V)
    • JESD8-5A (2.3 V to 2.7 V)
    • JESD8-C/JESD36 (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Parametrics

Type number Package name
74LVCH16373ADL SSOP48

Package

All type numbers in the table below are discontinued.

Type number Orderable part number, (Ordering code (12NC)) Status Marking Package Package information Reflow-/Wave soldering Packing
74LVCH16373ADL 74LVCH16373ADL,112
(935238480112)		 Obsolete LVCH16373A Standard Procedure Standard Procedure SOT370-1
SSOP48
(SOT370-1) 		SOT370-1 SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE
Not available
74LVCH16373ADL,118
(935238480118)		 Obsolete LVCH16373A Standard Procedure Standard Procedure SOT370-1_118

Environmental information

All type numbers in the table below are discontinued.

Type number Orderable part number Chemical content RoHS RHF-indicator
74LVCH16373ADL 74LVCH16373ADL,112 74LVCH16373ADL rohs rhf rhf
74LVCH16373ADL 74LVCH16373ADL,118 74LVCH16373ADL rohs rhf rhf
Quality and reliability disclaimer

Series

Documentation (8)

File name Title Type Date
74LVC_LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Data sheet 2024-04-23
AN11009 Pin FMEA for LVC family Application note 2019-01-09
AN263 Power considerations when using CMOS and BiCMOS logic devices Application note 2023-02-07
lvch16373a lvch16373a IBIS model IBIS model 2013-04-09
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT370-1 plastic, shrink small outline package; 48 leads; 0.635 mm pitch; 15.9 mm x 7.5 mm x 2.8 mm body Package information 2020-04-21
SSOP-TSSOP-VSO-REFLOW Footprint for reflow soldering Reflow soldering 2009-10-08
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

Support

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Models

File name Title Type Date
lvch16373a lvch16373a IBIS model IBIS model 2013-04-09

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Interactive datasheet