Features and benefits
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Automotive product qualification in accordance with AEC-Q100 (Grade 1)
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Specified from -40 °C to +85 °C and from -40 °C to +125 °C
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Wide supply voltage range from 2.3 V to 3.6 V
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CMOS low power dissipation
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High noise immunity
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Overvoltage tolerant inputs to 3.6 V
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Low noise overshoot and undershoot < 10 % of VCC
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IOFF circuitry provides partial power-down mode operation
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Latch-up performance exceeds 100 mA per JESD 78 Class II
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Low static power consumption; ICC = 1.5 μA (maximum)
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Complies with JEDEC standards:
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JESD8-12 (0.8 V to 1.3 V)
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JESD8-11 (0.9 V to 1.65 V)
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JESD8-7 (1.65 V to 1.95 V)
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JESD8-5 (2.3 V to 2.7 V)
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JESD8C (2.7 V to 3.6 V)
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ESD protection:
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HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
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CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
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Parametrics
Type number | Product status | VCC(A) (V) | VCC(B) (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
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74AUP1T97GW-Q100 | Production | 2.3 - 3.6 | n.a. | CMOS | ± 4 | 3.9 | 1 | ultra low | -40~125 | 264 | 38.6 | 153 | TSSOP6 |
Package
Type number | Package | Package information | Reflow-/Wave soldering | Packing | Status | Marking | Orderable part number, (Ordering code (12NC)) |
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74AUP1T97GW-Q100 | TSSOP6 (SOT363-2) | SOT363-2 | SOT363-2_125 | Active | 59 | 74AUP1T97GW-Q100H ( 9356 911 79125 ) |
Environmental information
Type number | Orderable part number | Chemical content | RoHS | RHF-indicator | Leadfree conversion date |
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74AUP1T97GW-Q100 | 74AUP1T97GW-Q100H | 74AUP1T97GW-Q100 |
Documentation (6)
File name | Title | Type | Date |
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74AUP1T97_Q100 | Low-power configurable gate with voltage-level translator | Data sheet | 2023-07-17 |
Nexperia_document_guide_Logic_translators | Nexperia Logic Translators | Brochure | 2021-04-12 |
Nexperia_document_leaflet_Logic_X2SON_packages_062018 | X2SON ultra-small 4, 5, 6 & 8-pin leadless packages | Leaflet | 2018-06-05 |
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Leaflet | 2019-04-12 |
wlcsp6_74aup1t97uk_3d | wafer level chip-scale package; 6 bumps; 0.65 x 0.44 x 0.27 mm | Outline 3d | 2017-01-30 |
SOT363-2 | plastic thin shrink small outline package; 6 leads; body width 1.25 mm | Package information | 2022-11-21 |
Support
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Ordering, pricing & availability
Sample
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