74AUP1G00-Q100
Low-power 2-input NAND gate
The 74AUP1G00-Q100 is a single 2-input NAND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 0.8 V to 3.6 V
CMOS low power dissipation
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 Vto 2.7 V)
JESD8C (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Low static power consumption; ICC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Overvoltage tolerant inputs to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Parametrics
Type number | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Package name |
---|---|---|---|---|---|---|---|---|---|
74AUP1G00GW-Q100 | 0.8 - 3.6 | CMOS | ± 1.9 | 8.3 | 70 | 1 | ultra low | -40~125 | TSSOP5 |
Package
Type number | Orderable part number, (Ordering code (12NC)) | Status | Marking | Package | Package information | Reflow-/Wave soldering | Packing |
---|---|---|---|---|---|---|---|
74AUP1G00GW-Q100 | 74AUP1G00GW-Q100H (935690852125) |
Active | pA |
TSSOP5 (SOT353-1) |
SOT353-1 |
WAVE_BG-BD-1
|
SOT353-1_125 |
Environmental information
Type number | Orderable part number | Chemical content | RoHS | RHF-indicator |
---|---|---|---|---|
74AUP1G00GW-Q100 | 74AUP1G00GW-Q100H | 74AUP1G00GW-Q100 |
Documentation (10)
File name | Title | Type | Date |
---|---|---|---|
74AUP1G00_Q100 | Low-power 2-input NAND gate | Data sheet | 2023-07-11 |
Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
SOT353-1 | 3D model for products with SOT353-1 package | Design support | 2019-09-23 |
aup1g00 | 74AUP1G00 IBIS model | IBIS model | 2014-12-04 |
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Leaflet | 2019-04-12 |
Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
TSSOP5_SOT353-1_mk | plastic, thin shrink small outline package; 5 leads; 0.65 mm pitch; 2 mm x 1.25 mm x 0.95 mm body | Marcom graphics | 2018-07-25 |
SOT353-1 | plastic thin shrink small outline package; 5 leads; body width 1.25 mm | Package information | 2022-11-15 |
Nexperia_Selection_guide_2023 | Nexperia Selection Guide 2023 | Selection guide | 2023-05-10 |
WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
Support
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Ordering, pricing & availability
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