74AUP2G04-Q100
Low-power dual inverter
The 74AUP2G04-Q100 is a dual inverter. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Low static power consumption; ICC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Parametrics
Type number | VCC (V) | Logic switching levels | Output drive capability (mA) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Package name |
---|---|---|---|---|---|---|---|---|
74AUP2G04GW-Q100 | 0.8 - 3.6 | CMOS | ± 1.9 | 70 | 2 | ultra low | -40~125 | TSSOP6 |
Package
Type number | Orderable part number, (Ordering code (12NC)) | Status | Marking | Package | Package information | Reflow-/Wave soldering | Packing |
---|---|---|---|---|---|---|---|
74AUP2G04GW-Q100 | 74AUP2G04GW-Q100H (935307306125) |
Active | p4 |
TSSOP6 (SOT363-2) |
SOT363-2 | SOT363-2_125 |
Environmental information
Type number | Orderable part number | Chemical content | RoHS | RHF-indicator |
---|---|---|---|---|
74AUP2G04GW-Q100 | 74AUP2G04GW-Q100H | 74AUP2G04GW-Q100 |
Documentation (8)
File name | Title | Type | Date |
---|---|---|---|
74AUP2G04_Q100 | Low-power dual inverter | Data sheet | 2023-07-19 |
AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
AN11052 | Pin FMEA for AUP family | Application note | 2019-01-09 |
SOT363-2 | 3D model for products with SOT363-2 package | Design support | 2023-02-02 |
aup2g04 | aup2g04 IBIS model | IBIS model | 2015-09-06 |
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Leaflet | 2019-04-12 |
SOT363-2 | plastic thin shrink small outline package; 6 leads; body width 1.25 mm | Package information | 2022-11-21 |
Nexperia_Selection_guide_2023 | Nexperia Selection Guide 2023 | Selection guide | 2023-05-10 |
Support
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Ordering, pricing & availability
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