LSF0102-Q100
2-bit bidirectional multi-voltage level translator; open-drain; push-pull
The LSF0102-Q100 is a 2 channel bidirectional multi-voltage level translator for open-drain and push-pull applications. It supports up to 100 MHz up translation and ≥100 MHz down translation at ≤ 30 pF capacitive load. There is no need for a direction pin which minimizes system effort. The LSF0102-Q100 supports 5 V tolerant I/O pins for compatibility with TTL levels in a variety of applications. The ability to set up different voltage translation levels on each channel makes the device very flexible and suitable for a lot of different applications.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +125 °C
Bidirectional voltage translation with no direction pin
Up translation
≤ 100 MHz; CL = 30 pF
≤ 50 MHz; CL = 50 pF
Down translation
≥ 100 MHz; CL = 30 pF
≥ 50 MHz; CL = 50 pF
Hot insertion
Bidirectional voltage level translation between:
0.95 V and 1.8 V, 2.5 V, 3.3 V and 5.0 V
1.2 V and 1.8 V, 2.5 V, 3.3 V and 5.0 V
1.8 V and 2.5 V, 3.3 V and 5.0 V
2.5 V and 3.3 V and 5.0 V
3.3 V and 5.0 V
Low standby current
5 V tolerant I/O pins to support TTL
Low RON provides less signal distortion
High-impedance I/O pins for EN = Low.
Flow-through pinout for easy PCB trace routing.
Latch-up performance exceeds 100 mA per JESD78 class II level A
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Applications
GPIO, MDIO, PMBus, SMBus, SDIO, UART, I2C, and other interfaces in Telecom infrastructure
Industrial
Personal computing
Parametrics
Type number | VCC(A) (V) | VCC(B) (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | Nr of bits | Power dissipation considerations | Tamb (°C) | Package name |
---|---|---|---|---|---|---|---|---|---|
LSF0102DC-Q100 | 0.95 - 5.0 | 0.95 - 5.0 | CMOS | + 64 | 0.7 | 2 | low | -40~125 | VSSOP8 |
LSF0102DP-Q100 | 0.95 - 5.0 | 0.95 - 5.0 | CMOS | + 64 | 0.7 | 2 | low | -40~125 | TSSOP8 |
Package
Type number | Orderable part number, (Ordering code (12NC)) | Status | Marking | Package | Package information | Reflow-/Wave soldering | Packing |
---|---|---|---|---|---|---|---|
LSF0102DC-Q100 | LSF0102DC-Q100H (935691018125) |
Active | h2 |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 | |
LSF0102DP-Q100 | LSF0102DP-Q100H (935691058125) |
Active | h2 |
TSSOP8 (SOT505-2) |
SOT505-2 | SOT505-2_125 |
Environmental information
Type number | Orderable part number | Chemical content | RoHS | RHF-indicator |
---|---|---|---|---|
LSF0102DC-Q100 | LSF0102DC-Q100H | LSF0102DC-Q100 | ||
LSF0102DP-Q100 | LSF0102DP-Q100H | LSF0102DP-Q100 |
Documentation (10)
File name | Title | Type | Date |
---|---|---|---|
LSF0102_Q100 | 2-bit bidirectional multi-voltage level translator; open-drain; push-pull | Data sheet | 2024-06-25 |
AN90050 | Pin FMEA for LSF family | Application note | 2023-12-14 |
Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
SOT765-1 | 3D model for products with SOT765-1 package | Design support | 2020-01-22 |
SOT505-2 | 3D model for products with SOT505-2 package | Design support | 2019-01-18 |
lsf0102 | LSF0102 IBIS model | IBIS model | 2020-04-14 |
Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
VSSOP8_SOT765-1_mk | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Marcom graphics | 2017-01-28 |
SOT765-1 | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Package information | 2022-06-03 |
SOT505-2 | plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm body | Package information | 2022-06-03 |
Support
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Ordering, pricing & availability
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